Switched-capacitor integrator

ABSTRACT

A switched-capacitor integrator eliminates noise caused by the switching of an input signal. For this purpose, the integrator includes a switched-capacitor unit for providing a capacitor with one of a first and a second input voltage in response to clock signals, a reference voltage providing unit for receiving a reference voltage and outputting an amplified reference voltage, a switching noise eliminating unit for maintaining an output of the reference voltage providing unit at a stabilized voltage level, an operational amplifying unit for receiving an output of the switched-capacitor unit as its negative input and the output of the reference voltage providing unit passed through the switching noise eliminating unit as its positive input and a feedback capacitor for feeding back an output of the operational amplifying unit to the negative input.

FIELD OF THE INVENTION

[0001] The present invention relates to a switched-capacitor integrator and, more particularly, to a switched-capacitor integrator for eliminating switching noise.

DESCRIPTION OF RELATED ART

[0002]FIG. 1A shows a circuit diagram of a typical integrator which is a basic filter circuit in an electronic circuit implementing filters. The integrator includes an operational amplifier A for amplifying voltage passing through its negative input node and for outputting an output voltage signal V_(out)(t), a feedback capacitor C₂ connecting the negative input node and an output node of the operational amplifier A and a resistor R₁ connecting a voltage input node of V_(in)(t) and the negative input node of the operational amplifier A. The transfer function and frequency characteristics of the integrator are H(s)=−1/R₁C₂*1/s.

[0003] When embodying the integrator of FIG. 1A in an integrated circuit, the resistor and capacitor of the integrator have accuracy errors of approximately 5% and 1%, respectively. These errors vary substantially with the operation environment, such as manufacturing process, temperature and use time, making it difficult to obtain accurate and reliable frequency characteristics. Therefore, in order to solve the above problem of the integrated circuit, there has been introduced a switched-capacitor circuit illustrated in FIG. 1B.

[0004] The switched-capacitor circuit will be explained with reference to FIG. 1B.

[0005] First of all, φ₁ and φ₂ are non-overlapping two-phase clock signals and a charge of Q₁=C₁*V₁ is stored in C₁ while φ₁ has a ‘1’ state. After one half period of the two-phase clock signals φ₁ and φ₂, wherein φ₂ has a ‘1’ state, C₁ is coupled with V₂ and, thus, a charge of Q₂=C₁*V₂ is stored in C₁. At this time, a charge of ΔQ=C₁(V₁−V₂) flows from the switched-capacitor C₁. Therefore, during the one clock period T, an average current of I=ΔQ/T=C₁(V₁−V₂)/T, which can be represented as (V₁−V₂)/R_(eq), flows from V₁ to V₂. Accordingly, the switched-capacitor circuit can be implemented by using an equivalent resistor R_(eq).

[0006] The switched-capacitor circuit can be readily integrated on a single chip through the use of a CMOS manufacturing process and has advantages of removing resistors and reducing power consumption. As a result, it can be used in almost any analog integrated filter. Further, a filter using the switched-capacitor circuit expresses the frequency characteristics of the integrator as a capacitance ratio and, therefore, it can provide high accuracy and operational reliability.

[0007] Referring to FIG. 1C, there is provided an integration circuit using a switched-capacitor.

[0008] The switched-capacitor integrator includes an operational amplifier A, a capacitor C₂ connected between a negative input node and an output node of the operational amplifier A, two switches S₁ and S₂ and a capacitor C₁ connected between a connection node of the two switches S₁ and S₂ and a ground voltage node. The switches S₁ and S₂ alternately perform a switching operation in response to the non-overlapping two-phase clock signals φ₁ and φ₂ as described above.

[0009] When forming a capacitor on a practical integrated circuit, parasitic capacitance occurs at both ends of the capacitor, which has an influence on the frequency characteristics of the integrator. In order to exclude this influence, both ends of the parasitic capacitance should be connected to a certain voltage, a ground voltage source or the input or output node of the operational amplifier A at any clock signal φ₁ or φ₂ to avoid their floating states.

[0010]FIG. 1D illustrates a switched-capacitor integrator performing an integration operation regardless of the parasitic capacitance through the use of the above scheme.

[0011] The switched-capacitor integrator of FIG. 1D further includes switches S₃ and S₄ at both ends of the capacitor C1 shown in FIG. 1C. Switches S₃ and S₄ operate alternately in response to the non-overlapping two-phase clock signals φ₁ and φ₂, respectively, like the switches S₁ and S₂.

[0012] Herein, capacitors C_(P1L), C_(P1R), C_(P2L) and C_(P2R) represent parasitic capacitance caused at both ends of the capacitors C₁ and C₂, respectively.

[0013] At first, when considering the parasitic capacitors C_(P1L) and C_(P1R) related to the capacitor C₁, one end of the parasitic capacitor C_(P1L) is connected to an input voltage V_(in) if an actuated clock input, e.g., having a ‘1’ state, is φ₁ and, thus, the switch S₁ is on. On the other hand, the other end of the parasitic capacitor C_(P1L) is attached to the ground voltage source if the actuated clock input is φ₂ and, thus, the switch S₄ is on. In the mean time, one end of the parasitic capacitor C_(P1R) is coupled to the ground voltage source if the actuated clock input is φ₁ and, thus, the switch S₃ is on. On the other hand, the other end of the parasitic capacitor C_(P1R) is attached to a negative input node of the operational amplifier A if the actuated clock input is φ₂ and, thus, the switch S₂ is on. As a result, both ends of the parasitic capacitor are connected to a certain voltage, such as V_(in), the ground voltage source or the input node of the operational amplifier A, at any actuated clock signal φ₁ or φ₂.

[0014] Meanwhile, the parasitic capacitor C_(P2L) of capacitor C₂ is always connected to a virtual ground voltage source and the parasitic capacitor C_(P2R) of capacitor C₂ is attached to the output node of the operational amplifier A. Therefore, the parasitic capacitors C_(P2L) and C_(P2R) do not have an influence on the operation of the integrator.

[0015] Referring to FIG. 2, there is shown a circuit diagram of a switched-capacitor integrator including a reference voltage unit in addition to the integrator of FIG. 1D.

[0016] The switched-capacitor integrator comprises a first and a second switch SW₁ and SW₂ providing input signals V_(a) and V_(b), respectively, to one end of an input capacitor C₁, a first operational amplifier A1 receiving a reference voltage V_(c) as its positive input and whose output node is connected with its negative input node, a third switch SW₃ connecting the output node N₂ of the first operational amplifier A1 with the other end N₁ of the input capacitor C₁, a second operational amplifier A2 receiving a signal from the input capacitor C₁ through a fourth switch SW₄ as its positive input and the output of the first operational amplifier A1 as its negative input, and a feedback capacitor C₂ connecting an output signal V_(out) with the negative input of the second operational amplifier A2.

[0017] Hereinafter, the operation of the switched-capacitor integrator employing the reference voltage unit will be explained with reference to FIG. 2. As described above, φ₁ and φ₂ are the non-overlapping two-phase clock signals. Furthermore, the first and third switches SW₁ and SW₃ operate in response to the first phase clock signal φ₁ and the second and fourth switches SW₂ and SW₄ operate under the control of the second phase clock signal φ₂.

[0018] That is, if the first phase clock signal φ₁ is actuated and, thus, the first and third switches SW₁ and SW₃ are on, a charge of C₁(V_(a)−V_(c)) is stored in the input capacitor C1. On the other hand, if the second phase clock signal φ₂ is actuated and, thus, the second and fourth switches SW₂ and SW₄ are on, a charge of C1(V_(b)−V_(c)) is stored in the input capacitor C₁. Therefore, during one clock period, a charge of {C₁(V_(a)−V_(c))}−{C₁(V_(b)−V_(c))}=C₁(V_(a)−V_(b))moves from the input capacitor C₁ to the feedback capacitor C₂ according to the law of conservation of quantity of electric charge.

[0019] When the actuated clock signal changes from φ₂ to φ₁, the amount of charge stored in the input capacitor C₁ cannot change suddenly from C₁(V_(b)−V_(c)) to C₁(V_(a)−V_(c)) and, therefore, the instant voltage of the input capacitor C₁ is maintained at V_(b)−V_(c). However, since the input voltage changes from V_(b) to V_(a) at the moment when the actuated clock signal becomes φ₁, the voltage at the output node N₂ of the first operational amplifier changes instantaneously to maintain the instant voltage across the capacitor C₁ at V_(b)−V_(c), causing switching noise to occur.

[0020] Since this switching noise influences all of the characteristics of the integration circuit, it should be minimized. Further, since the node N₂ where the switching noise occurs is connected to the positive input of the second operational amplifier A2, it is necessary to eliminate the switching noise.

SUMMARY OF THE INVENTION

[0021] It is, therefore, a primary object of the present invention to provide a switched-capacitor integrator capable of eliminating noises caused by the switching of an input signal.

[0022] In accordance with the present invention, there is provided a switched-capacitor integrator including a resistor and a capacitor connected to an input node of an operational amplifier to eliminate switching noise caused when a voltage at the input node of the operational amplifier is instantaneously changed. As a result, since the voltage at the input node varies according to a time constant τ=RC, the switching noise can be eliminated by adjusting the resistance R and the capacitance C. This allows the voltage at the input node of the operational amplifier to be virtually constant.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0024]FIGS. 1A to 1D show circuit diagrams of conventional integrators;

[0025]FIG. 2 provides a circuit diagram of a conventional integrator including a reference voltage unit in addition to the integrator shown in FIG. 1D;

[0026]FIG. 3 illustrates a circuit diagram of a switched-capacitor integrator in accordance with an embodiment of the present invention; and

[0027]FIG. 4 is a waveform diagram showing a voltage signal of the inventive integrator of FIG. 3 and that of the conventional integrator at a positive input node of a second operational amplifier.

DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0029] Referring to FIG. 3, there is illustrated a switched-capacitor integrator in accordance with a preferred embodiment of the present invention.

[0030] The switched-capacitor integrator comprises a switched-capacitor unit 300 for supplying a first or a second input voltage V_(a) or V_(b) to a capacitor therein by using switches operating in response to clock signals, a reference voltage providing unit 200 for receiving a reference voltage V_(c) and outputting an amplified reference voltage, a switching noise eliminating unit 100 for maintaining an output of the reference voltage providing unit 200 at a stabilized voltage level, an operational amplifier A2 for receiving an output of the switched-capacitor unit 300 as its negative input and the output of the reference voltage providing unit 200 passed through the switching noise eliminating unit 100 as its positive input and a feedback capacitor C₂ for feeding back an output V_(out) to the negative input node N₄ of the operational amplifier A2.

[0031] The switched-capacitor unit 300 includes a first capacitor C1 and a first switch SW₁ for providing the first input voltage V_(a) to one end N₅ of the first capacitor C₁, a second switch SW₂ for supplying the second input voltage V_(b) to the one end N₅ of the first capacitor C₁, a third switch SW₃ for connecting the other end N₁ of the first capacitor C₁ with an output node N₂ of the reference voltage providing unit 200 and a fourth switch SW₄ for attaching the other end N₁ of the first capacitor C₁ to the negative input node N₄ of the operational amplifier A2.

[0032] The reference voltage providing unit 200 employs a first operational amplifier A1 which receives the reference voltage V_(c) as its positive input and whose output is fed back to its negative input.

[0033] The switching noise eliminating unit 100 contains a resistor R₃ connected between the output node N₂ of the operational amplifier A1 and the positive input node N₃ of the operational amplifier A2, and a second capacitor C₃ located between the positive input node N₃ of the operational amplifier A2 and a ground voltage node.

[0034]FIG. 4 provides a waveform diagram showing a voltage signal (b) of the inventive integrator in FIG. 3 and a voltage signal (a) of the conventional integrator at the positive input node of the operational amplifier A2.

[0035] Hereinafter, the operation of the inventive switched-capacitor integrator will be described with reference to FIGS. 3 and 4.

[0036] As mentioned before, φ₁ and φ₂ are the non-overlapping two-phase clock signals. The first and third switches SW₁ and SW₃ operate in response to the first phase clock signal φ₁ and the second and fourth switches SW₂ and SW₄ operate in response to the second phase clock signal φ₂.

[0037] When the first phase clock signal φ₁ is enabled and, thus, the first and third switches SW₁ and SW₃ are on, a charge of C₁(V_(a)−V_(c))is stored in the first capacitor C₁. On the other hand, when the second phase clock signal φ₂ is enabled and, thus, the second and fourth switches SW₂ and SW₄ are on, a charge of C₁(V_(b)−V_(c)) is stored in the first capacitor C₁. Therefore, during one clock period T, the amount of charge moving from the first capacitor C₁ to the feedback capacitor C₂ is {C₁(V_(a)−V_(c))}−{C₁(V_(b)−V_(c))}=C₁(V_(a)−V_(b)) according to the law of conservation of quantity of electric charge.

[0038] When the actuated clock signal changes from φ₂ to φ₁, the amount of charge stored in the first capacitor C₁ cannot change suddenly from C₁(V_(b)−V_(c)) to C₁(V_(a)−V_(c)) and, therefore, the input capacitor C₁ maintains an instant voltage of V_(b)−V_(c). However, since the input voltage changes from V_(b) to V_(a) at the moment when the actuated clock signal becomes φ₁, the voltage at the output node N₂ of the first operational amplifier A1 changes instantaneously to maintain the instant voltage across the capacitor C₁ at V_(b)−V_(c). As a result, switching noise occurs.

[0039] However, in accordance with the present invention, since the switching noise eliminating unit 100 is employed between the output node N₂ of the reference voltage providing unit 200 and the positive input node N₃ of the second operational amplifier A2, problems do not occur in operating the integrator despite the sudden variation of voltage at node N₂ and it is possible to maintain a constant voltage at node N₃.

[0040] Namely, since the voltage at node N₃ is dependent on a time constant τ=RC of the resistor R₃ and the capacitor C3, although the voltage at node N₂ is instantaneously changed, the voltage at node N₃ can be maintained almost unchanged by adjusting the resistance R and the capacitance C of the resistor R₃ and the capacitor C₃, respectively.

[0041] Finally, since the switching noise eliminating unit 100 removes high frequency noise, it can be constructed using a low-pass filter.

[0042] As described above, in accordance with the present invention, it is possible to eliminate the switching noise caused in the integration circuit and, thus, guarantee a stable circuit operation.

[0043] While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims. 

What is claimed is:
 1. A switched-capacitor integrator comprising: switched-capacitor means for providing a capacitor with one of a first and a second input voltage in response to clock signals; reference voltage providing means for receiving a reference voltage and outputting an amplified reference voltage; switching noise eliminating means for maintaining an output of the reference voltage providing means at a stabilized voltage level; operational amplifying means for receiving an output of the switched-capacitor means as its negative input and the output of the reference voltage providing means passed through the switching noise eliminating means as its positive input; and a feedback capacitor for feeding back an output of the operational amplifying means to said negative input.
 2. The switched-capacitor integrator as recited in claim 1, wherein the switching noise eliminating means comprises a low-pass filter.
 3. The switched-capacitor integrator as recited in claim 2, wherein the switching noise eliminating means includes: a resistor connected between the output node of the reference voltage providing means and the positive input node of the operational amplifying means; and a capacitor connected between the positive input node of the operational amplifying means and a ground voltage node.
 4. The switched-capacitor integrator as recited in claim 1, wherein the reference voltage providing means comprises an operational amplifier which receives the reference voltage as its positive input and whose output is fed back to its negative input node.
 5. The switched-capacitor integrator as recited in claim 1, wherein the switched-capacitor means includes: a capacitor; a first switch for providing the first input voltage to a first end of said capacitor; a second switch for supplying the second input voltage to the first end of said capacitor; a third switch for connecting a second end of said capacitor to the output node of the reference voltage providing means; and a fourth switch for connecting the second end of said capacitor to the negative input node of the operational amplifying means. 